An integrated circuit (e.g., an electronic circuit formed on a substrate of semiconductor material) may operate at faster speeds and/or may be physically smaller as semiconductor technology improves (e.g., transistors forming the integrated circuit may have less delay because of smaller physical size). As the integrated circuit becomes faster and physically smaller, the integrated circuit may dissipate more dynamic power (e.g., power when the integrated circuit is powered and is switching). The dynamic power may increase because a larger number of transistors may be formed in a given area of the substrate.
One way to reduce the dynamic power consumed is to reduce a supply voltage that powers the integrated circuit. However, this reduction may adversely affect a performance (e.g. maximum clock speed) of the integrated circuit. The integrated circuit may include multiple sub-circuits controlled by different power supplies to minimize the dynamic power consumed by the integrated circuit (e.g., non-critical paths may be powered by lower power supplies).
However, by having multiple sub-circuits controlled by different power supplies, the integrated circuit may dissipate more static power (e.g., power when the integrated circuit is powered but not switching). The static power may increase because gate oxides may become thinner in small transistors that form the integrated circuit and because of a voltage ramp time between the multiple sub-circuits.
The level shifter circuit may be an electronic component that can help deliver an output that is at a same voltage as a power domain. In addition, the level shifter may help to minimize the static power in the integrated circuit by providing an output voltage at a desired voltage with minimum transition voltages (e.g., while a voltage level is adjusting to the output voltage, transition voltages can create leakage because n-type and p-type transistors of the level shifter circuit may simultaneously be active during the transition voltages because they may be partially on at the transition voltages).
However, the integrated circuit may not operate with a faster clock frequency (e.g., currently 3.8 GHz in many applications though in future generations of application specific integrated circuits it may be faster) when the level shifter circuit is used because the level shifter circuit can have an inherent duty cycle error (e.g., a duty cycle may be a ratio of time a clock signal is in a high state as a percentage of total time in a period). The inherent duty cycle error can cause a number of problems because a component (e.g., a memory) coupled to the integrated circuit (e.g., and/or sub-circuits forming the integrated circuit) may expect a constant duty cycle (e.g., often 50%), and the inherent duty cycle error can cause erroneous data to be transmitted to the component (e.g., the duty cycle may be skewed to 45% because of the inherent duty cycle error).
In addition, the integrated circuit having the level shifter circuit may not internally communicate reliable data when the faster clock frequency is used because a delay in a flip-flop of the integrated circuit may be larger than an ‘on’ time of an output of the level shifter circuit (e.g., the output of the level shifter circuit in a high state) having the inherent duty cycle error. Therefore, the inherent duty cycle error can cause the integrated circuit to fail when the faster clock frequency is used and/or can impose a limit on a maximum clock speed of the integrated circuit.